1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having multiple channel regions and a semiconductor device fabricated thereby.
2. Description of the Related Art
Semiconductor device widely employs discrete devices such as a field effect transistor (FET) as a switching device. On-current flowing through a channel between a source and a drain of the transistor determines the operating speed of the device. Typically, a gate electrode, and source and drain regions are formed in a device-forming region of a substrate, i.e., an active region, so that a planar-type transistor is formed. The planar-type transistor typically has a planar channel between its source and drain. On-current of the planar-type transistor is proportional to the width of the active region, and is inversely proportional to the distance between the source and drain, i.e., the gate length. Accordingly, in order to increase the operating speed of the device by increasing the on-current, the gate length should be decreased, and the width of the active region should be increased. However, as deep device integration increases, further increase in the width of the active region of planar devices becomes impossible in the planar-type transistor.
Recently, a phase change memory device has been proposed. A unit cell of the phase change memory device includes a switching device (i.e., a cell transistor) and a data storage element serially connected to the switching device. The data storage element has a lower electrode electrically connected to the switching device, and a phase change material layer contacting the lower electrode. In general, the lower electrode operates as a heater. When a write current (i.e., a program current) flows through the switching device and the lower electrode, a Joule heat is generated at an interface between the phase change material layer and the lower electrode. Such Joule heat transforms the phase change material layer into an amorphous state or crystalline state. The phase transition of the phase change material layer requires a large programming current of about 1 mA. Accordingly, the cell transistor should be designed to have current drivability enough to provide the write current. However, in order to enhance the current drivability of the cell transistor, an area occupied by the cell transistor should be increased. In particular, when the cell transistor is a planar-type Metal Oxide Semiconductor (MOS) transistor, the write current is directly associated with a channel width of the planar-type MOS transistor.
A technique for increasing the channel width of the MOS transistor is proposed in U.S. Pat. No. 6,872,647 B1 entitled “METHOD FOR FORMING MULTIPLE FINS IN A SEMICONDUCTOR DEVICE” to Yu et al., and incorporated herein by reference.